Recently, large-scale integrated circuits (LSIs) including a plurality of data transmission ports which support high speed data transmission standards have been used in, for example, server devices and network devices. Exemplary high speed data transmission standards are 10 Gigabit Ethernet (the IEEE 802.3ae standard; Ethernet is a registered trademark) and Peripheral Component Interconnect (PCI)-Express.
For the high speed data transmission, high speed and high performance, and at the same time, low cost and low power consumption LSIs are in increasing demand. In order to achieve such LSIs, data transmitter and receiver circuits becomes more populated and thereby a single LSI has a plurality of data transmission ports (i.e., channels).
A data receiver circuit typically includes a receiver circuit and a phase-locked loop (PLL) circuit which generates clocks. The PLL circuit occupies a large part of a circuit area of the LSI and is high in power consumption as compared with other circuits. Therefore, if a PLL circuit is provided in each channel in a structure in which a plurality of data transmission ports are mounted on a single LSI, the PLL circuits occupy an even larger part of the entire area of the LSI and increase the power consumption. It is therefore common in a data receiver circuit to share a single PLL circuit by receiver circuits of a plurality of channels.
In the field of deserializer networks for high speed serial data receivers mounted on programmable logic device integrated circuits, networks for converting serial data into parallel data having arbitrary data widths have been proposed.
In a hetero transceiver architecture to provide extensive programmability of a programmable logic device, a high speed serial data transceiver network has been proposed which includes some channels that may operate at a data rate to a first, relatively low maximum data rate and other channels that may operate at a data rate to a second, relatively high maximum data rate.
The followings are reference documents.                Document 1: Japanese Laid-Open Patent Publication No. 2007-43718        Document 2: Japanese Laid-Open Patent Publication No. 2007-282183        
Hereinafter, an exemplary related art data transmitter and receiver circuit will be described.
A data receiver circuit 900 illustrated in FIG. 10 includes a PLL circuit 901 and a plurality of receiver circuits 902.
In the data receiver circuit 900, a plurality of inputs of serial data #11 to #14 are converted into parallel data #11 to #14 in each of the receiver circuits 902, and the converted parallel data #11 to #14 is transmitted.
In the following description, the channel #11 supports conversion of an input of the serial data #11 into the parallel data #11. Other channels #12 to #14 are similar to the channel #1.
The PLL circuit 901 transmits predetermined clock signals to each of the receiver circuits 902. The PLL circuit 901 transmits clock signals Clk to each of the receiver circuits 902. Upon reception of the serial data #11 to #14, each of the receiver circuits 902 converts the serial data #11 to #14 to the parallel data #11 to #14 in accordance with the clock signals Clk and transmits the obtained parallel data #11 to #14.
The data receiver circuit 910 illustrated in FIG. 11 includes a plurality of PLL circuits 911, a plurality of receiver circuits 912 and a plurality of switch circuits (SW) 913. A plurality of PLL circuits 911 are represented as, for example, a PLL circuit 911A which outputs high speed clocks ClkH and a PLL circuit 911B which outputs low speed clocks ClkL.
The PLL circuit 911A generates the high speed clocks ClkH and transmits the generated high speed clocks ClkH to the switch circuits 913. The PLL circuit 911B generates the low speed clocks ClkL and transmits the generated low speed clocks ClkL to the switch circuits 913. Here, the high speed clocks ClkH are high frequency clocks as compared with the low speed clocks ClkL like the data receiver circuit 900 illustrated in FIG. 10.
The switch circuits 913 are switches for selecting clocks to be supplied to the receiver circuits 912 from among a plurality of clock inputs. The switch circuits 913 receive the high speed clocks ClkH generated by the PLL circuit 911A and the low speed clocks ClkL generated by the PLL circuit 911B. Each of the switch circuits 913 selects the high speed clocks ClkH or the low speed clocks ClkL in accordance with received clock selection signals Clk #21 to #24 and transmits the selected clocks to the corresponding receiver circuit 912.
The receiver circuits 912 receive serial data #21 to #24. Each of the receiver circuits 912 converts the serial data #21 to #24 into parallel data #21 to #24 in accordance with the clocks transmitted from the switch circuits 913.
Since the data receiver circuit 910 includes a plurality of PLL circuits 911 each of which supplies clocks which support the different data rates, each channel may select a data rate independently in accordance with the clock selection signals Clk #21 to #24. This allows the data receiver circuit 910 to convert the received serial data #21 to #24 into the parallel data #21 to #24 at the data rate set for each channel.
It is desired in many systems that the data rate may be selected independently for each connection destination of the channel. Data may be received at different data rates for each transmission port in a data transmission circuit provided with a plurality of data transmission ports (i.e., channels).
The data receiver circuit 900 illustrated in FIG. 10 includes a plurality of channels #11 to #14 in accordance with a plurality of receiver circuits 902. Since a single PLL circuit 901 is shared by a plurality of channels #11 to #14 in the data receiver circuit 900, the data rates of all the parallel data #11 to #14 of the channels are the same. That is, since independent selection of the high speed clock ClkH or the low speed clock may not be made in each channel in the data receiver circuit 900, all the channels may employ a single data rate in accordance with a single clock. Such a less flexible configuration allows no independent selection of the data rate for each connection destination of the channel.
Since each channel independently corresponds to a data rate at which data is transmitted in the data receiver circuit 910 illustrated in FIG. 11, a plurality of PLL circuits 911 for generating clocks supporting different data rates are required. In addition, since each channel independently selects an output from a plurality of PLL circuits 911 and supplies the output to a receiver circuit 912, a plurality of switch circuits 913 corresponding to each of the channels are required for switching clocks output from a plurality of PLL circuits 911.
Thus, the PLL circuits 911 and the switch circuits 913 occupy an increased circuit area in the data receiver circuit 910. In addition, the data receiver circuit 910 requires a plurality of PLL circuits 911 and a switch circuit 913 which switches clocks output from the PLL at a high speed so as to correspond to operation speed. Power consumption thus increases. Use of switch circuit 913 for switching the output clocks increases jitter, which decreases timing accuracy for sampling serial data and increases occurrence of data receiving error.
As described above, in a circuit configuration in which a data receiver circuit includes a single PLL circuit which supplies a single clock, data rates of a plurality of channels may not be independently set.
In a circuit configuration in which a data receiver circuit includes a plurality of PLL circuit, on the other hand, which supplies a plurality of clocks, there are also problems that the PLL circuits and the switch circuits occupy a large part of the area of the LSI and increase in power consumption.